module bitrev (
    input  sck,
    input  ss, // low active
    input  mosi,
    output miso
);
    parameter RX=1'b0,TX=1'b1;
    reg       state,dout;
    reg [7:0] data;   
    reg [3:0] cnt; 
    wire reset = ss;

    always@(posedge sck or posedge reset) begin
        if (reset)               
            data <= 8'h00;
        else if(state == RX && cnt < 'd8)
            data <= { data[6:0], mosi };          
    end
    always@(posedge sck or posedge reset) begin
        if (reset)               
            cnt  <= 'b0;
        else if(cnt < 'd8)
            cnt  <= cnt+1'b1;
        else
            cnt  <= 'b0;            
    end 
    always@(posedge sck or posedge reset) begin
        if (reset)               
            state<= RX;
        else if(cnt == 'd8)
            state<= TX;
    end  
    always@(negedge sck or posedge reset) begin
        if (reset)               
            dout <= 'h0;
        else if(state == TX || cnt == 'd8)
            dout<= data[cnt[2:0]+1];
    end        
    
assign miso = ss? 1'b1: dout;

endmodule
